• Skip to primary navigation
  • Skip to main content
  • Skip to footer

Vonoff

SkyKo Comics and videos about Semiconductor and nanotechnology | 반도체 만화

  • HOME
  • COMICS & VIDEOS
  • ABOUT
  • CONTACT
Home / Comics / 기억을 쫓아서-#3 – DRAM 새로운 3D power scaling 시대로

기억을 쫓아서-#3 – DRAM 새로운 3D power scaling 시대로

December 1, 2017 By sky Leave a Comment

Summary

저항변화를 이용하는 차세대메모리인 STT-MRAM/PCRAM/ReRAM가 개발되고 있는 가운데 DRAM은 새로운 3D power scaling 시대로 나아갈 희망을 갖는다.

  • select language:
  • KR
  • EN
유망한 차세대메모리-PcRAM, STT-MRAM,RERAM
P1
차세대메모리 Big3 : PCRAM, STT-MRAM, ReRAM
차세대메모리는 저항기반 비휘발성 메모리
P2
차세대메모리는 저항기반 비휘발성 메모리
캐패시터로 인한 D램 미세화 공정의 기술한계
P3
*Short Channel Effect(단채널 효과): Effects occurred when the channel length of MOSTETs is the same order of magnitude as the depletion-layer widths of the source and drain junction
무어의 법칙은 언제 무너지나?
P4
DRAM은 계속진화할 것
무어의 법칙 새롭게 변신-3D Power Scaling
P5
Moore's Law는 3D power scaling으로 변신

Please consider becoming a sponsor of my work
  • Scroll to:
  • Ep1
  • Ep2
  • Ep3
  • Next

Share this post : on Twitter on Facebook on LinkedIn

Reference

  1. Ping Er-Xuan. AMAT. 3D Architecture and Interconnect for Emerging Memory Technologies. SPCC 2016.
  2. "How new Non Volatile Memories Are Enabling Disruptive Computing Architectures?". Denis Dutoit, CEA-LETI. Flash memory summit, 2017.
  3. Hutcheson G.D. (2009) The Economic Implications of Moore’s Law. In: Huff H.R. (eds) Into the Nano Era. Springer Series in Materials Science, vol 106. Springer, Berlin, Heidelberg.
  4. “ITRS Reports.” International Technology Roadmap for Semiconductors, www.itrs2.net/itrs-reports.html.
  5. "Energy Aware Memory Technology and New Memory System Hierarchy" Frank Koch. Samsung Semiconductor Europe GmbH. 2013.
  6. "An Overview and Future Challenges of High Density DRAM for 20nm and Beyond." Yoosang Hwang, et al. Samsung. SSDM 2012.
  7. "Memory Scaling: A Systems Architecture Perspective." Onur Mutlu, Carnegie Mellon University. 2013.

Share this post : on Twitter on Facebook on LinkedIn

Related posts:

A trip down memory lane -#2: The sorrow of DRAM scaling challenge comics of "A Trip Down memory Lane"-featured image-1A trip down memory lane -#1: Memory to reduce latency gap A trip down memory lane -#3 : DRAM vs. emerging memories Default Thumbnail기억을 쫓아서-#1 – CPU와 메모리간 병목현상 극복 A_Trip_Down_Memory_Lane-featured-2기억을 쫓아서-#2 – 새로운 차세대메모리 등장 Nanofabrication at Harvard CNS-Ep1-Kr하버드대 CNS 나노팹에서 소자제조 – Ep1
(Getting ready)

Filed Under: Comics, Memory technology, Nanotechnology Tagged With: 3d power scaling, capacitor, DRAM, dram transistor evolution, D램, emerging memory, Moore's law 3.0, pcram, reram, stt-mram, 공정미세화 한계, 무어의법칙, 차세대메모리

Reader Interactions

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Footer

  • skyonsky@gmail.com
  • About
  • Comics

All work © Sky Ko -